1. Field of the Invention
This invention generally relates to a processing system for a digital video signal. This invention particularly relates to an encoder and a decoder for processing a digital video signal in a digital recording and reproducing apparatus such as a digital VTR (video tape recorder).
2. Description of the Prior Art
The recording sections of digital VTR's include a signal processor for compressing a video signal by an efficient encoding technique using orthogonal transform. Such a signal processor has a series combination of an orthogonal transform circuit, a variable-length encoding circuit, an error correction encoding circuit, and a record encoding circuit.
The orthogonal transform circuit subjects an input digital video signal to given orthogonal transform such as two-dimensional DCT (discrete cosine transform). For example, pixel-corresponding components of the input video signal which form one field or one frame are grouped into a given number of blocks each having 8 by 8 adjacent pixels (8 pixels in the horizontal direction and 8 pixels in the vertical direction) according to the JPEG standards. The orthogonal transform is executed on every block. The orthogonal transform generates 8 by 8 pieces of data (DCT coefficient data) per block. Zigzag scanning rearranges 8 by 8 pieces of data into a sequence of data which is outputted from the orthogonal transform circuit to the variable-length encoding circuit.
The variable-length encoding circuit has a section for quantizing the output data of the orthogonal transform circuit by referring to a plurality of discrete quantization levels. The variable-length encoding circuit also has a section for encoding the quantization-resultant data into words of a given variable-length code such as a two-dimensional Huffman code. The variable-length encoding circuit outputs the code data to the error correction encoding circuit.
The error correction encoding circuit subjects the output data from the variable-length encoding circuit to given encoding such as Reed-Solomn encoding for error correction. The error correction encoding circuit is followed by the record encoding circuit. The record encoding circuit subjects the output data from the error correction encoding circuit to given encoding such as I-NRZI encoding for recording.
The rate of compression of video data by such a signal processor affects the quality of an image represented by the processing-resultant data. A low compression rate and a high compression rate are chosen for a high-quality image and a low-quality image respectively. As the compression rate decreases and hence the image quality increases, the signal processor is required to handle a greater number of bits of data per unit time.
The reproducing sections of the digital VTR's include a series combination of circuits having functions inverse with respect to the functions of the circuits in the recording sections thereof.